View C501G-1E_5066875.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

C501
8-Bit Single-Chip Microcontroller
User's Manual 04.97
ht
tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/
Edition 04.97 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
C501 User's Manual Revision History : Previous Releases : Page (previous version) general Chapter 1 1-2 3-4 to 3-6 4-2 6-10 6-15 follo. 6-23 follo. 6-30 follo. chapter 7 8-2 chapter 9 9-6, 9-9 9-12 9-17 9-18 Chapter 1 1-2 3-2 to 3-7 4-4 4-5 6-10 6-15, 6-16 6-22, 6-23 6-29 chapter 7 8-4 chapter 9 chapter 10 10-3 10-6,10-8 10-10 10-13 10-15/16 10-18 10-21 chapter 11 Page (new version)
04.97 02.96, 08.94, 08.93 (Original Version) Subjects (changes since last revision)
C501G-1E OTP version included (new chapter 9, AC/DC characteristics now in chapter 10) Several figures: update with C501-1E signal names and definitions; P-MQFP-44 package (pin configuration and pin numbers) added Feature list is updated Actualized design of the SFR tables Figure 4-1 moved Description of enhanced hooks emulation concept added Figure 6-6 corrected Improved timer 0/1 register description Improved timer 2 register description Improved serial port register description Improved description of the interrupt related functions: all enable, control, and request register bits now included Table 8-1 moved into chapter 8.4 New chapter 9 "OTP Memory Operation of the C501-1E" included Old chapter 9 ("Device Specifications") is now chapter 10 "DC Characteristics for C501-1E" included Characteristics for "External Clock Drive" on three pages moved below "Ext. Data Memory Characteristics" Old figure 7 moved to figure 10-4 New chapter 10.8 "OTP Programming and Verification Characteristics" Figure 10-9: M-QFP-44 pin numbers for XTAL1/XTAL2 added M-QFP-44 package outline added Manual index information added
C501
Table of Contents
Page
1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 5 5.1 5.2 6 6.1 6.1.1 6.1.1.1 6.1.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . 4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . 6-7 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Read-Modify-Write Feature of Ports 1,2 and 3 . . . . . . . . . . . . . . . . . . . . . 6-11 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
I-1
Semiconductor Group
C501
Table of Contents
Page
6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.4 6.3.5 6.3.6 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 9.4 9.5
Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Auto-Reload (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Baud Rates Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 Using Timer 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Power Saving Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 State of Pins in Software Initiated Power Saving Modes . . . . . . . . . . . . . . . 8-4 OTP Memory Operation of the C501-1E . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Quick-Pulse Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Encryption Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 OTP Memory Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Semiconductor Group
I-2
C501
Table of Contents
Page
10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11
Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 DC Characteristics for C501-L / C501-1R . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 DC Characteristics for C501-1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 AC Characteristics for C501-L / C501-1R / C501-1E . . . . . . . . . . . . . . . . 10-5 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 . . . . . . . . . . . 10-7 AC Characteristics for C501-L40 / C501-1R40 . . . . . . . . . . . . . . . . . . . . . 10-9 ROM Verification Characteristics for C501-1R . . . . . . . . . . . . . . . . . . . . . 10-14 OTP Programming and Verification Characteristics for C501-1E . . . . . . 10-15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Semiconductor Group
I-3
Introduction C501
1
Introduction
The C501-L, C501-1R, and C501-1E described in this document are compatible (also pincompatible) with the 80C52 and can be used in typical 80C52 applications. The C501-1R contains a non-volatile 8Kx8 read-only program memory, a volatile 256x8 read/write data memory, four ports, three 16-bit timers/counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip. The term C501 refers to all versions within this specification unless otherwise noted.
Power Saving Modes T0 T2 T1
RAM 256 x 8
Port 0
/O
Port 1 CPU USART Port 2
/O
/O
8K x 8 ROM (C501-1R) 8K x 8 OTP (C501-1E)
Port 3
/O
MCA03238
Figure 1-1 C501G Functional Units
Semiconductor Group
1-1
Introduction C501
Listed below is a summary of the main features of the C501:
* * * * * * * * * * * * *
Fully compatible to standard 8051 microcontroller Versions for 12/24/40 MHz operating frequency Program memory : completely external (C501-L) 8K x 8 ROM (C501-1R) 8K x 8 OTP memory (C501-1E) 256 x 8 RAM Four 8-bit ports Three 16-bit timers / counters (timer 2 with up/down counter feature) USART Six interrupt sources, two priority levels Power saving modes Quick Pulse programming algorithm (C501-1E only) 2-Level program memory lock (C501-1E only) P-DIP-40, P-LCC-44, and P-MQFP-44 package Temperature ranges : SAB-C501 TA : 0 C to 70 C SAF-C501 TA : - 40 C to 85 C
VCC
VSS
XTAL1 XTAL2
Port 0 8-Bit Digital /O Port 1 8-Bit Digital /O
RESET EA /VPP ALE/PROG PSEN
C501
Port 2 8-Bit Digital /O Port 3 8-Bit Digital /O
MCL03217
Figure 1-2 Logic Symbol
Semiconductor Group
1-2
Introduction C501
1.1
Pin Configuration
This section shows the pin configuration of the C501 in the P-LCC-44, P-DIP-40, and P-MQFP-44 packages.
P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 N.C VCC
6 P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
C501
18 19 20 21 22 23 24 25 26 27 28
WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS N.C. P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12
MCP03214
Figure 1-3 Pin Configuration P-LCC-44 Package (top view)
Semiconductor Group
1-3
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
Introduction C501
T2/P1.0
1 2 3 4 5 6 7 8 9 10
40 39 38 37 36 35 34 33 32 31
VCC
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1
C501
11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21
MCP03215
VSS
Figure 1-4 Pin Configuration P-DIP-40 Package (top view)
Semiconductor Group
1-4
Introduction C501
P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC N.C. P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4
34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C501 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 N.C. VSS XTAL1 XTAL2 RD/P3.7 WR/P3.6
P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
MCP03216
Figure 1-5 Pin Configuration P-MQFP-44 Package (top view)
Semiconductor Group
1-5
Introduction C501
1.2
Pin Definitions and Functions
This section describes all external signals of the C501 with its function. Table 1-1 Pin Definitions and Functions Symbol P1.0 - P1.7 2-9 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 1-8 40-44, 1-3, I/O Port 1 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 1 also contains the timer 2 pins as secondary function. The output latch corresponding to a secondary function must be pro-grammed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 1, as follows: P1.0 T2 Input to counter 2 P1.1 T2EX Capture - Reload trigger of timer 2 / Up-Down count I/O*) Function
2 3
*) I = Input O = Output
1 2
40 41
Semiconductor Group
1-6
Introduction C501
Table 1-1 Pin Definitions and Functions (cont'd) Symbol P3.0 - P3.7 11, 13-19 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 10-17 5, 7-13 I/O Port 3 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 3 also contains the interrupt, timer, serial port 0 and external memory strobe pins which are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RxD receiver data input (asynchronous) or data input output (synchronous) of serial interface 0 P3.1 TxD transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 P3.2 INT0 interrupt 0 input/timer 0 gate control P3.3 INT1 interrupt 1 input/timer 1 gate control P3.4 T0 counter 0 input P3.5 T1 counter 1 input P3.6 WR the write control signal latches the data byte from port 0 into the external data memory P3.7 RD the read control signal enables the external data memory to port 0 I/O*) Function
11
10
5
13
11
7
14 15 16 17 18
12 13 14 15 16
8 9 10 11 12
19
17
13
*) I = Input O = Output
Semiconductor Group
1-7
Introduction C501
Table 1-1 Pin Definitions and Functions (cont'd) Symbol XTAL2 20 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 18 14 - XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. Port 2 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-up resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. I/O*) Function
XTAL1
21
19
15
-
P2.0 - P2.7 24-31
21-28
18-25
I/O
*) I = Input O = Output
Semiconductor Group
1-8
Introduction C501
Table 1-1 Pin Definitions and Functions (cont'd) Symbol PSEN 32 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 29 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. For the C501-1E this pin is also the program pulse input (PROG) during OTP memory programming. External Access Enable When held at high level, instructions are fetched from the internal ROM (C501-1R and C501-1E) when the PC is less than 2000H. When held at low level, the C501 fetches all instructions from external program memory. For the C501-L this pin must be tied low. This pin also receives the programming supply voltage VPP during OTP memory programming (C501-1E) only). I/O*) Function
RESET
10
9
4
I
ALE/PROG 33
30
27
I/O
EA/VPP
35
31
29
I
*) I = Input O = Output
Semiconductor Group
1-9
Introduction C501
Table 1-1 Pin Definitions and Functions (cont'd) Symbol P0.0 - P0.7 43-36 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 39-32 37-30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-up resistors when issuing 1s. Port 0 also outputs the code bytes during program verification in the C501-1R and C501-1E. External pull-up resistors are required during program verification. Circuit ground potential Supply terminal for all operating modes No connection I/O*) Function
VSS VCC
N.C.
22 44 1, 12, 23, 34
20 40 -
16 38 6, 17, 28, 39
- - -
*) I = Input O = Output
Semiconductor Group
1-10
Fundamental Structure C501
2
Fundamental Structure
The C501 is fully compatible to the standard 8051 microcontroller family. It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 8051 microcontroller family, the C501 incorporates some enhancements in the timer 2 and fail save mechanism unit. Figure 2-6 shows a block diagram of the C501.
V CC V SS
XTAL1 XTAL2
C501
RAM
C501-1R : ROM C501-1E : OTP 8K x 8
OSC & Timing
256 x 8
RESET ALE/PROG PSEN EA/VPP
CPU Timer 0 Timer 1 Port 1 Timer 2 Port 2 Interrupt Unit Serial Channel (USART) Port 3 Port 3 8-Bit Digit. /O Port 2 8-Bit Digit. /O
Port 0 8-Bit Digit. /O
Port 0
Port 1 8-Bit Digit. /O
MCB03219
Figure 2-6 Block Diagram of the C501
Semiconductor Group
2-1
Fundamental Structure C501
2.1
CPU
The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12 MHz crystal, 58% of the instructions execute in 1.0 s (24 MHz : 500 ns, 40 MHz : 300 ns). The CPU (Central Processing Unit) of the C501 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.
Accumulator ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.
Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.
Semiconductor Group
2-2
Fundamental Structure C501
Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1
Reset Value : 00H LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00 H-07H Bank 1 selected, data address 08 H-0FH Bank 2 selected, data address 10 H-17H Bank 3 selected, data address 18 H-1FH
OV F1 P
Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control.
Semiconductor Group
2-3
Fundamental Structure C501
2.2
CPU Timing
A machine cycle of the C501 consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logically operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-7 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-7 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C501 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-7 c) and d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.
Semiconductor Group
2-4
Fundamental Structure C501
Figure 2-7 Fetch Execute Sequence
Semiconductor Group
2-5
Memory Organization C501
3
Memory Organization
The C501 CPU manipulates operands in the following four address spaces: - - - - up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area
Figure 3-1 illustrates the memory address spaces of the C501.
FFFF H
FFFF H
External
External
Indirect Address FF H Internal RAM 2000 H 1FFF H Internal (EA = 1) External (EA = 0) 0000 H "Code Space" 0000 H "Data Space" Internal RAM 80 H
Direct Address Special Function Register 7F H 00 H FF H 80 H
"Internal Data Space"
MCD03224
Figure 3-1 C501 Memory Map
Semiconductor Group
3-1
Memory Organization C501
3.1
Program Memory, "Code Space"
The C501-1R/-1E has 8 Kbytes of read-only/OTP program memory, while the C501-L has no internal program memory. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C501 executes out of internal program memory unless the address exceeds 1FFFH. Locations 2000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C501 fetches all instructions from the external program memory. 3.2 Data Memory, "Data Space"
The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. 3.3 General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 and RS1, select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage.
Semiconductor Group
3-2
Memory Organization C501
3.4
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in table 3-1 and table 3-2. In table 3-2 they are organized in groups which refer to the functional blocks of the C501. Table 3-3 illustrates the contents (bits) of the SFRs.
Semiconductor Group
3-3
Memory Organization C501
Table 3-2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP IE IP P0 P1 P2 P3 PCON 2) SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD T2CON T2MOD RC2H RC2L TH2 TL2 Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byt Timer 2 High Byte Timer 2 Low Byte Power Control Register Address E0H 1) F0H 1) 83H 82H D0H 1) 81H A8H1) B8H 1) 80H 1) 90H 1) A0H 1) B0H 1) 87H 99H 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H C8H 1) C9H CBH CAH CDH CCH 87H Contents after Reset 00H 00H 00H 00H 00H 07H 0X000000B 3) XX000000B 3) FFH FFH FFH FFH 0XXX0000B 3) XXH 3) 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 3) 00H 00H 00H 00H 0XXX0000B 3)
Interrupt System Ports
Serial Channel Timer 0 / Timer 1
Timer 2
Pow. Sav. PCON 2) Modes
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved
Semiconductor Group
3-4
Memory Organization C501
Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H2) P0 81H 82H 83H 87H SP DPL DPH PCON FFH 07H 00H 00H 0XXX0000B 00H 00H 00H 00H 00H 00H FFH 00H XXH FFH 0X000000B FFH XX000000B 00H XXXXXXX0B 00H 00H 00H 00H .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
.6 .6 .6 .6
.5 .5 .5 .5 - TF0 M1 .5 .5 .5 .5 .5 SM2 .5 .5 ET2 T1 PT2 RCLK - .5 .5 .5 .5
.4 .4 .4 .4 - TR0 M0 .4 .4 .4 .4 .4 REN .4 .4 ES T0 PS TCLK - .4 .4 .4 .4
.3 .3 .3 .3 GF1 IE1 GATE .3 .3 .3 .3 .3 TB8 .3 .3 ET1 INT1 PT1
.2 .2 .2 .2 GF0 IT1 C/T .2 .2 .2 .2 .2 RB8 .2 .2 EX1 INT0 PX1
.1 .1 .1 .1 PDE IE0 M1 .1 .1 .1 .1 .1 TI .1 .1 ET0 TxD PT0 C/T2 - .1 .1 .1 .1
.0 .0 .0 .0 IDLE IT0 M0 .0 .0 .0 .0 .0 RI .0 .0 EX0 RxD PX0 CP/ RL2 DCEN .0 .0 .0 .0
SMOD - TF1 GATE .7 .7 .7 .7 .7 SM0 .7 .7 EA RD - TF2 - .7 .7 .7 .7 TR1 C/T .6 .6 .6 .6 .6 SM1 .6 .6 - WR - EXF2 - .6 .6 .6 .6
88H2) TCON 89H 8AH 8BH TMOD TL0 TL1
8CH TH0 8DH TH1 90H 99H
2)
P1 SBUF
98H2) SCON A0H2) P2 A8H2) IE B0H2) P3 B8H2) IP C8H2) T2CON C9H T2MOD CAH RC2L CBH RC2H CCH TL2 CDH TH2
EXEN2 TR2 - .3 .3 .3 .3 - .2 .2 .2 .2
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers
Semiconductor Group
3-5
Memory Organization C501
Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Content Bit 7 after Reset1) D0H2) PSW E0H2) ACC F0H2) B 00H 00H 00H CY .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AC .6 .6
F0 .5 .5
RS1 .4 .4
RS0 .3 .3
OV .2 .2
F1 .1 .1
P .0 .0
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers
Semiconductor Group
3-6
External Bus Interface C501
4
External Bus Interface
The C501 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed. 4.1 Accessing External Memory
It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FF H to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods.
Semiconductor Group
4-1
External Bus Interface C501
a) S1 ALE
One Machine Cycle S2 S3 S4 S5 S6 S1
One Machine Cycle S2 S3 S4 S5 S6
PSEN RD PCH OUT INST. IN PCL OUT PCL OUT valid b) S1 ALE INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN (A) without MOVX
P2
P0
One Machine Cycle S2 S3 S4 S5 S6 S1
One Machine Cycle S2 S3 S4 S5 S6
PSEN (B) with MOVX PCH OUT INST. IN PCL OUT PCL OUT valid INST. IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST. IN
MCT03220
RD
P2
P0
Figure 4-1 External Program Memory Execution
Semiconductor Group
4-2
External Bus Interface C501
4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated.
Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: - whenever signal EA is active (low) or - whenever the program counter (PC) contains a number that is larger than 1FFF H. This requires the ROM-less version C501-L to have EA wired low to allow the lower 8K program bytes to be fetched from external memory. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). When the C501 executes instructions from external program memory, port 2 is at all times dedicated to output the high-order address byte. This means that port 0 and port 2 of the C501 can never be used as general-purpose I/O. This means that port 0 and port 2 of the C501-L can never be used as general-purpose I/O. This also applies to the C501-1R/1E when they are operating with external program memory only.
Semiconductor Group
4-3
External Bus Interface C501
4.2
PSEN, Program Store Enable
The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 ALE, Address Latch Enable
The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 4-1 b). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. 4.4 Overlapping External Data and Program Memory Spaces
In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C501 the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
Semiconductor Group
4-4
External Bus Interface C501
4.5
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too (not true for the C509-l, because it lacks internal program memory). Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology TM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System Interface to Emulation Hardware
SYSCON PCON TCON
RESET EA ALE PSEN
RSYSCON RPCON RTCON
EH-IC
C500 MCU
Optional I/O Ports
Port 0 Port 2
Enhanced Hooks Interface Circuit
Port 3
Port 1
RPort 2 RPort 0
TEA TALE TPSEN
Target System Interface
MCS02647
Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
1
"Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens.
Semiconductor Group
4-5
System Reset C501
5 5.1
System Reset Hardware Reset
The hardware reset function incorporated in the C501 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. The RESET input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VSS via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the RESET pin for a specific time to effect a complete reset. A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0, 1, 2 and 3 default in FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1, 2 and 3) output at one (1). The content of the internal RAM of the C501 is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off.
Semiconductor Group
5-1
System Reset C501
5.2
Hardware Reset Timing
This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. The RESET signal must be active for at least two machine cycles; after this time the C501 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles.
One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2
RESET
P0
PCL OUT PCH OUT
Inst. in
PCL OUT PCH OUT
P2
ALE
MCT02092
Figure 5-3 CPU Timing after Reset
Semiconductor Group
5-2
On-Chip Peripheral Components C501
6
On-Chip Peripheral Components
I/O Ports The C501 has four 8-bit I/O portst. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. 6.1 Parallel I/O
6.1.1 Port Structures Digital I/O The C501 allows for digital I/O on 32 lines grouped into 4 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P3 are performed via their corresponding special function registers P0 to P3.
Semiconductor Group
6-1
On-Chip Peripheral Components C501
Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 4 I/O-ports. The bit latch (one bit in the port's SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P3) activate the "read-latch" signal, while others activate the "read-pin" signal.
Read Latch
Int. Bus Write to Latch
D Port Latch CLK
Q Port Driver Circuit Port Pin
Q
MCS01822
Read Pin
Figure 6-4 Basic Structure of a Port Circuitry
Semiconductor Group
6-2
On-Chip Peripheral Components C501
Port 1, 2 and 3 output drivers have internal pullup FET's (see figure 6-5). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-5: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional".
Read Latch
VCC
Internal Pull Up Arrangement Q Bit Latch CLK Pin
Int. Bus Write to Latch
D
Q
n1
MCS01823
Read Pin
Figure 6-5 Basic Output Driver Circuit of Ports 1, 2, and 3
Semiconductor Group
6-3
On-Chip Peripheral Components C501
In fact, the pullups mentioned before and included in figure 6-5 are pullup arrangements as shown in figure 6-6. One n-channel pulldown FET and three pullup FETs are used:
Delay = 1 State
VCC
=1
_ <1
p1
p2
p3 Port Pin
Q
n1
VSS
Input Data (Read Pin) =1 =1
MCS03230
Figure 6-6 Output Driver Circuit of Ports 1 to 5 and 7 - The pulldown FET n1 is of n-channel type. It is a very strong driver transistor which is capable of sinking high currents (IOL); it is only activated if a "0" is programmed to the port pin. A short circuit to VCC must be avoided if the transistor is turned on, since the high current might destroy the FET. This also means that no "0" must be programmed into the latch of a pin that is used as input. - The pullup FET p1 is of p-channel type. It is activated for two oscillator periods (S1P1 and S1P2) if a 0-to-1 transition is programmed to the port pin, i.e. a "1" is programmed to the port latch which contained a "0". The extra pullup can drive a similar current as the pulldown FET n1. This provides a fast transition of the logic levels at the pin. - The pullup FET p2 is of p-channel type. It is always activated when a "1" is in the port latch, thus providing the logic high output level. This pullup FET sources a much lower current than p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input level. - The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g when used as input. In this configuration only the weak pullup FET p2 is active, which sources the current IIL . If, in addition, the pullup FET p3 is activated, a higher current can be sourced (ITL). Thus, an additional power consumption can be avoided if port pins are used as inputs with a low level applied. However, the driving capability is stronger if a logic high level is output.
Semiconductor Group
6-4
On-Chip Peripheral Components C501
The described activating and deactivating of the four different transistors results in four states which can be: - - - - input low state (IL), p2 active only input high state (IH) = steady output high state (SOH), p2 and p3 active forced output high state (FOH), p1, p2 and p3 active output low state (OL), n1 active
If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state. If the latch is loaded with "0", the pin will be in OL state. If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur. At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on pin is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will remain in this state or will switch to IH (=SOH) state. If it is is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3's trip point after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds the drive capability of p2 (IIL), the pin might remain in the IL state and provide a week "1" until the first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of the external circuitry. The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities. If the load exceeds IIL the pin can be forced to "1" by writing a "0" followed by a "1" to the port pin.
Semiconductor Group
6-5
On-Chip Peripheral Components C501
Port 0, in contrast to ports 1, 2 and 3, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-7) is used only when the port is emitting 1 s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required.
Addr./Data Read Latch Control &
VCC
=1 Int. Bus Write to Latch D Bit Latch CLK Q
Port Pin
Q
MUX
MCS02122
Read Pin
Figure 6-7 Port 0 Circuitry
Semiconductor Group
6-6
On-Chip Peripheral Components C501
6.1.1.1
Port 0 and Port 2 used as Address/Data Bus
As shown in figure 6-7 and below in figure 6-8, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P2 SFR remains unchanged while the P0 SFR has 1's written to it. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-7. When a 16-bit address is used, port 2 uses the additional strong pullups p1 to emit 1's for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity.
Read Latch Addr. Control
V CC
Internal Pull Up Arrangement
Int. Bus Write to Latch
D Bit Latch CLK
Q MUX Q =1
Port Pin
Read Pin
MCS02123
Figure 6-8 Port 2 Circuitry
Semiconductor Group
6-7
On-Chip Peripheral Components C501
6.1.2
Alternate Functions
The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-4. Figure 6-9 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1).
Read Latch
Alternate Output Function
VCC
Internal Pull Up Arrangement Pin
Int. Bus Write to Latch
D Bit Latch CLK
Q
&
Q
MCS01827
Read Pin
Alternate Input Function
Figure 6-9 Circuitry of Ports 1 and 3
Semiconductor Group
6-8
On-Chip Peripheral Components C501
Ports 1 and 3 are provided for several alternate functions, as listed in table 6-4: Table 6-4 Alternate Functions of Port 1 and 3 Port P1.0 P1.1 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Pin T2 T2EX RxD TxD INT0 INT1 T0 T1 WR RD Alternate Function Input to counter 2 Capture-reload trigger of timer 2 / up down count Serial port's receiver data input (asynchronous) or data input/output (synchronous) Serial port's transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external counter input Timer 1 external counter input External data memory write strobe External data momory read strobe
Semiconductor Group
6-9
On-Chip Peripheral Components C501
6.1.3 Port Handling 6.1.3.1 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-10 illustrates this port timing. lt must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain requirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once.
S4 P1 XTAL2 P2 P1
S5 P2 P1
S6 P2 P1
S1 P2 P1
S2 P2 P1
S3 P2
Input sampled: e.g. MOV A, P1
P1 active for 1 State (driver transistor)
Port
Old Data
New Data
MCT03231
Figure 6-10 Port Timing
Semiconductor Group
6-10
On-Chip Peripheral Components C501
6.1.3.2 Port Loading and Interfacing The output buffers of ports 1, 2 and 3 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be looked up in the C501 DC characteristics in chapter 10. The corresponding parameters are VOL and VOH. The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus. When used as inputs it must be noted that the ports 1, 2 and 3 are not floating but have internal pullup transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters ITL and IIL in the C501 DC characteristics specify these currents). Port 0 has floating inputs when used for digital input. 6.1.3.3 Read-Modify-Write Feature of Ports 1,2 and 3
Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-5. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, respectively, is performed by reading the SFR P0, P1, P2 and P3; for example, "MOV A, P3" reads the value from port 3 pins, while "ANL P3, #0AAH" reads from the latch, modifies the value and writes it back to the latch. It is not obvious that the last three instructions in table 6-5 are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch.
Semiconductor Group
6-11
On-Chip Peripheral Components C501
Table 6-5 Read-Modify-Write"- Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y,C CLR Px.y SETB Px.y Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit; e.g. CPL P3.0 Increment byte; e.g. INC P1 Decrement byte; e.g. DEC P1 Decrement and jump if not zero; e.g. DJNZ P3, LABEL Move carry bit to bit y of port x Clear bit y of port x Set bit y of port x
The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor (approx. 0.7 V, i.e. a logic low level!) and interpret it as "0". For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch. However, reading the latch rater than the pin will return the correct value of "1".
Semiconductor Group
6-12
On-Chip Peripheral Components C501
6.2
Timers/Counters
The C501 contains three 16-bit timers/counters, timer 0, 1, and 2, which are useful in many applications for timing and counting. In "timer" function, the timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the counter rate is 1/12 of the oscillator frequency. In "counter" function, the timer register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0, T1, or T2 (alternate functions of P3.4, P3.5 and P1.0 resp.). In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (24 oscillator periods) to recognize a 1to-0 transition, the maximum count rate is 124 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle.
Semiconductor Group
6-13
On-Chip Peripheral Components C501
6.2.1
Timer/Counter 0 and 1
Timer / counter 0 and 1 of the C501 are fully compatible with timer / counter 0 and 1 of the 80C51 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; Timer/ counter 1 in this mode holds its count. The effect is the same as setting TR1 = 0. External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD. In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted, this applies also to timer 1.
Semiconductor Group
6-14
On-Chip Peripheral Components C501
6.2.1.1
Timer/Counter 0 and 1 Registers
Totally six special function registers control the timer/counter 0 and 1 operation : - TL0/TH0 and TL1/TH1 - counter registers, low and high part - TCON and TMOD - control and mode select registers Special Function Register TL0 (Address 8AH) Special Function Register TH0 (Address 8CH) Special Function Register TL1 (Address 8BH) Special Function Register TH1 (Address 8DH) Bit No. MSB 7 .7 Reset Value : 00H Reset Value : 00H Reset Value : 00H Reset Value : 00H LSB 0 .0 TL0
6 .6
5 .5
4 .4
3 .3
2 .2
1 .1
8AH
8CH
.7
.6
.5
.4
.3
.2
.1
.0
TH0
8BH
.7
.6
.5
.4
.3
.2
.1
.0
TL1
8DH
.7
.6
.5
.4
.3
.2
.1
.0
TH1
Bit TLx.7-0 x=0-1
Function Timer/counter 0/1 low register Operating Mode Description 0 1 2 3 "TLx" holds the 5-bit prescaler value. "TLx" holds the lower 8-bit part of the 16-bit timer/counter value. "TLx" holds the 8-bit timer/counter value. TL0 holds the 8-bit timer/counter value; TL1 is not used.
THx.7-0 x=0-1
Timer/counter 0/1 high register Operating Mode Description 0 1 2 3 "THx" holds the 8-bit timer/counter value. "THx" holds the higher 8-bit part of the 16-bit timer/counter value "THx" holds the 8-bit reload value. TH0 holds the 8-bit timer value; TH1 is not used.
Semiconductor Group
6-15
On-Chip Peripheral Components C501
Special Function Register TCON (Address 88H) Bit No. MSB 7 8FH 88H TF1 6 8EH TR1 5 8DH TF0 4 8CH TR0 3 8BH IE1 2 8AH IT1 1 89H IE0
Reset Value : 00H LSB 0 88H IT0 TCON
The shaded bits are not used for controlling timer/counter 0 and 1.
Bit TR0 TF0
Function Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. Timer 0 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit Set/cleared by software to turn timer/counter 1 ON/OFF. Timer 1 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine.
TR1 TF1
Semiconductor Group
6-16
On-Chip Peripheral Components C501
Special Function Register TMOD (Address 89H) Bit No. 89H MSB 7 Gate
Reset Value : 00H LSB 0 M0 TMOD
6 C/T
5 M1
4 M0
3 Gate
2 C/T
1 M1
Timer 1 Control
Timer 0 Control
Bit GATE
Function Gating control When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set. Counter or timer select bit Set for counter operation (input from "Tx" input pin). Cleared for timer operation (input from internal system clock). Mode select bits M1 0 M0 0 Function 8-bit timer/counter: "THx" operates as 8-bit timer/counter "TLx" serves as 5-bit prescaler 16-bit timer/counter. "THx" and "TLx" are cascaded; there is no prescaler 8-bit auto-reload timer/counter. "THx" holds a value which is to be reloaded into "TLx" each time it overflows Timer 0 : TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1 : Timer/counter 1 stops
C/T
M1 M0
0 1
1 0
1
1
Semiconductor Group
6-17
On-Chip Peripheral Components C501
6.2.1.2
Mode 0
Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by32 prescaler. Figure 6-11 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1's to all 0's, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in figure 6-11. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3).
OSC
/ 12 C/T = 0 TL0
(5 Bits)
TH0
(8 Bits)
Interrupt TF0
C/T = 1 P3.4/T0 Control TR0
_ <1
Gate
=1
&
P3.2/INTO
MCS02143
Figure 6-11 Timer/Counter 0, Mode 0: 13-Bit Timer/Counter
Semiconductor Group
6-18
On-Chip Peripheral Components C501
6.2.1.3
Mode 1
Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-12.
OSC
/ 12 C/T = 0 TL0
(8 Bits)
TH0
(8 Bits)
Interrupt TF0
P3.4/T0
C/T = 1 Control TR0
_ <1
Gate
=1
&
P3.2/INTO
MCS02095
Figure 6-12 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter
Semiconductor Group
6-19
On-Chip Peripheral Components C501
6.2.1.4
Mode 2
Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-13. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.
Figure 6-13 Timer/Counter 0,1, Mode 2: 8-Bit Timer/Counter with Auto-Reload
Semiconductor Group
6-20
On-Chip Peripheral Components C501
6.2.1.5
Mode 3
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate counters. The logic for mode 3 on timer 0 is shown in figure 6-14. TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself.
OSC
/ 12
f OSC /12
C/T = 0 TL0
(8 Bits)
Interrupt TF0
P3.4/T0
C/T = 1 Control TR1
_ <1
Gate
=1
&
P3.2/INT0
f OSC /12
Control
TH0
(8 Bits)
Interrupt TF1
TR1
MCS02096
Figure 6-14 Timer/Counter 0, Mode 3: Two 8-Bit Timers/Counters
Semiconductor Group
6-21
On-Chip Peripheral Components C501
6.2.2
Timer/Counter 2
Timer 2 is a 16-bit timer / counter which can operate as timer or counter. It has three operating modes: - 16-bit auto-reload mode (up or down counting) - 16-bit capture mode - Baudrate generator for the serial interface The modes are selected by bits in the SFR T2CON (C8H) as shown in table 6-6: Table 6-6 Timer/Counter 2 - Operating Modes RXCLK + TXCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 Mode 16-bit auto-reload 16-bit capture Baud rate generator (OFF)
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2 (P1.0). In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscilllator frequency. To ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.
Semiconductor Group
6-22
On-Chip Peripheral Components C501
6.2.2.1
Timer 2 Registers
Totally six special function registers control the timer/counter 2 operation : - TL2/TH2 and RC2L/RC2H - counter and reload/capture registers, low and high part - T2CON and T2MOD - control and mode select registers Special Function Register TL2 (Address CCH) Special Function Register TH2 (Address CDH) Special Function Register RC2L (Address CAH) Special Function Register RC2H (Address CBH) Bit No. MSB 7 .7 Reset Value : 00H Reset Value : 00H Reset Value : 00H Reset Value : 00H LSB 0 LSB TL2
6 .6
5 .5
4 .4
3 .3
2 .2
1 .1
CCH
CDH
MSB
.6
.5
.4
.3
.2
.1
.0
TH2
CAH
.7
.6
.5
.4
.3
.2
.1
LSB
RC2L
CBH
MSB
.6
.5
.4
.3
.2
.1
.0
RC2H
Bit TL2.7-0 TH2.7-0 RC2L.7-0 RC2H.7-0
Function Timer 2 value low byte The TL2 register holds the 8-bit low part of the 16-bit timer 2 count value. Timer 2 value high byte The TH2 register holds the 8-bit high part of the 16-bit timer 2 count value. Reload register low byte CRCL is the 8-bit low byte of the 16-bit reload register of timer 2. Reload register high byte CRCH is the 8-bit high byte of the 16-bit reload register of timer 2.
Semiconductor Group
6-23
On-Chip Peripheral Components C501
Special Function Register T2CON (Address C8H) MSB CFH TF2
Reset Value : 00H LSB C8H
Bit No. C8H
CEH EXF2
CDH RCLK
CCH
CBH
CAH TR2
C9H
TCLK EXEN2
C/T2 CP/RL2 T2CON
Bit TF2
Function Timer 2 Overflow Flag. Set by a timer 2 overflow. Must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. Timer 2 External Flag. Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1, SFR T2MOD) Receive Clock Enable. When set, causes the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. RCLK = 0 causes timer 1 overflows to be used for the receive clock. Transmit Clock Enable. When set, causes the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. TCLK = 0 causes timer 1 overflow to be used for the transmit clock. Timer 2 External Enable. When set, allows a capture or reload to occur as a result of a negative transition on pin T2EX (P1.1) if timer 2 is not being used to clock the serial port. EXEN2 = 0 causes timer 2 to ignore events at T2EX. Start / Stop Control for Timer 2. TR2 = 1 starts timer 2. Timer or Counter Select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). Capture /Reload Select. CP/RL2 = 1 causes captures to occur an negative transitions at pin T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when timer 2 overflows or negative transitions occur at pin T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow.
EXF2
RCLK
TCLK
EXEN2
TR2 C/T2
CP/RL2
Semiconductor Group
6-24
On-Chip Peripheral Components C501
Special Function Register T2MOD (Address C9H) Bit No. C9H MSB 7 -
Reset Value : XXXXXXX0B LSB 0 DCEN T2MOD
6 -
5 -
4 -
3 -
2 -
1 -
The shaded bits are not used for controlling timer 2.
Bit - DCEN
Function Not implemented, reserved for future use. Down Counter Enable When set, this bit allows timer 2 to be configured as an up/down counter.
Semiconductor Group
6-25
On-Chip Peripheral Components C501
6.2.2.2
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by a bit named DCEN (Down Counter Enable, SFR T2MOD, 0C9H). When DCEN is set, timer 2 can count up or down depending on the value of pin T2EX (P1.1). Figure 6-15 shows timer 2 automatically counting up when DCEN = 0. In this mode there are two options selectable by bit EXEN2 in SFR T2CON.
Figure 6-15 Timer 2 Auto-Reload Mode (DCEN = 0) If EXEN2 = 0, timer 2 counts up to FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RC2H and RC2L. The values in RC2H and RC2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at the external input T2EX (P1.1). This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an timer 2 interrupt if enabled. Setting the DCEN bit enables timer 2 to count up or down as shown in figure 6-16. In this mode the T2EX pin controls the direction of count.
Semiconductor Group
6-26
On-Chip Peripheral Components C501
Figure 6-16 Timer 2 Auto-Reload Mode (DCEN = 1) A logic 1 at T2EX makes timer 2 count up. The timer will overflow at FFFF H and set the TF2 bit. This overflow also causes the 16-bit value in RC2H and RC2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes timer 2 count down. Now the timer underflows when TH2 and TL2 equal the values stored in RC2H and RC2L. The underflow sets the TF2 bit and causes FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever timer 2 overflows or underflows. This bit can be used as a 17th bit of resolution if desired. In this operating mode, EXF2 does not flag an interrupt. Note: P1.1/T2EX is sampled during S5P2 of every machine cycle. The next increment/decrement of timer 2 will be done during S3P1 in the next cycle.
Semiconductor Group
6-27
On-Chip Peripheral Components C501
6.2.2.3 Capture In the capture mode there are two options selected by bit EXEN2 in SFR T2CON. If EXEN2 = 0, timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in SFR T2CON. This bit can be used to generate an interrupt. If EXEN2 = 1, timer 2 still does the above, but with added feature that a 1-to-0 transition at external input T2EX causes the current value in TH2 and TL2 to be captured into RC2H and RC2L, respectively. In addition, the transition at T2EX causes bit EXF2 in SFR T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in figure 6-17.
Figure 6-17 Timer 2 in Capture Mode The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1 in SFR T2CON. It will be described in conjunction with the serial port.
Semiconductor Group
6-28
On-Chip Peripheral Components C501
6.3
Serial Interface
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receivebuffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes (one synchronous mode, three asynchronous modes): Mode 0, Shift Register (Synchronous) Mode: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 data bits are transmitted/ received: (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. (See section 6.3.4 for more detailed information) Mode 1, 8-Bit USART, Variable Baud Rate: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in special function register SCON. The baud rate is variable. (See section 6.3.5 for more detailed information) Mode 2, 9-Bit USART, Fixed Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can be assigned to the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. (See section 6.3.6 for more detailed information) Mode 3, 9-Bit USART, Variable Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable.(See section 6.3.6 for more detailed information) In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incomming start bit if REN = 1. The serial interface also provides interrupt requests when transmission or reception of a frames have been completed. The corresponding interrupt request flags are TI or RI, resp. See chapter 7 of this user manual for more details about the interrupt structure. The interrupt request flags TI and RI can also be used for polling the serial interface, if the serial interrupt is not to be used (i.e. serial interrupt not enabled).
Semiconductor Group
6-29
On-Chip Peripheral Components C501
6.3.1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is beeing addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the incoming data bytes. SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 6.3.2 Serial Port Registers The serial port control and status register is the special function register SCON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive TB8 and RB8), and the serial port interrupt bits (TI and RI). SBUF is the receive and transmit buffer of serial interface. Writing to SBUF loads the transmit register and initiates transmission. Reading out SBUF accesses a physically separate receive register.
Semiconductor Group
6-30
On-Chip Peripheral Components C501
Special Function Register SCON (Address 98H) Special Function Register SBUF (Address 99H) Bit No. MSB 9FH 98H SM0 7 99H 9EH SM1 6 9DH SM2 5 9CH REN 4 9BH TB8 3 9AH RB8 2 99H TI 1
Reset Value : 00H Reset Value : XXH LSB 98H RI 0 SBUF SCON
Serial Interface Buffer Register
Bit SM0 SM1
Function Serial port 0 operating mode selection bits SM0 0 0 1 1 SM1 0 1 0 1 Selected operating mode Serial mode 0 : Shift register, fixed baud rate (fOSC/6) Serial mode 1 : 8-bit UART, variable baud rate Serial mode 2 : 9-bit UART, fixed baud rate (fOSC/16 or fOSC/32) Serial mode 3 : 9-bit UART, variable baud rate
SM2
Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. Enable receiver of serial port Enables serial reception. Set by software to enable serial reception. Cleared by software to disable serial reception. Serial port transmitter bit 9 TB8 is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. Serial port receiver bit 9 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Serial port transmitter interrupt flag TI is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. TI must be cleared by software. Serial port receiver interrupt flag RI is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (exception see SM2). RI must be cleared by software.
REN
TB8
RB8
TI
RI
Semiconductor Group
6-31
On-Chip Peripheral Components C501
6.3.3 Baud Rates Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators have to provide a "baud rate clock" to the serial interface which - there divided by 16 - results in the actual "baud rate". However, all formulas given in the following section already include the factor and calculate the final baud rate. Further, the abrevation fOSC refers to the external clock frequency (oscillator or external input clock operation). The baud rate of the serial port is controlled by bit SMOD which is located in the special function register PCON as shown below. Special Function Register PCON (Address 87H) Bit No. 87H MSB 7 SMOD Reset Value : 0XXX0000B LSB 0 IDLE PCON
6 -
5 -
4 -
3 GF1
2 GF0
1 PDE
The shaded bits are not used for controlling the baud rate. Bit SMOD Function Double baud rate When set, the baud rate of serial interface in modes 1, 2, 3 is doubled. After reset this bit is cleared.
Mode 0 The baud rate in mode 0 is fixed: Mode 0 baud rate = oscillator frequency/12 = fOSC/12 Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON. If SMOD = 0 (which is the value on reset), the baud rate is fOSC/64. If SMOD = 1, the baud rate is fOSC/ 32. Mode 2 baud rate = 2SMOD/64x(fOSC) Modes 1 and 3 The baud rates in mode 1 and 3 are determined by the timer overflow rate. These baud rates can be determined by timer 1 or by timer 2 or by both (one for transmit and the other for receive).
Semiconductor Group
6-32
On-Chip Peripheral Components C501
6.3.3.1
Using Timer 1 to Generate Baud Rates
When timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows: Modes 1,3 baud rate = 2SMOD/32x(timer 1 overflow rate) The timer 1 interrupt should be disabled in this application. The timer itself can be configured for either "timer" or "counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD=0010B). In that case, the baud rate is given by the formula Modes 1,3 baud rate = 2SMOD/32xfOSC/ [12x(256-TH1)] One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of TMOD = 0001 B), and using the timer 1 interrupt to do a 16-bit software reload. Table 6-7 lists commonly used baud rates and how they can be obtained from timer 1. Table 6-7 Timer 1 Generated Commonly Used Baud Rates Baud Rate
fOSC
SMOD C/T
Timer 1 Mode X X 2 2 2 2 2 2 2 1 Reload Value X X FFH FDH FDH FAH F4H E8H 72H FEEBH
Mode 0 max: 1 MHz Mode 2 max: 375 K Modes 1, 3: 62.5 K 19.2 K 9.6 K 4.8 K 2.4 K 1.2 K 110 110
12 MHz 12 MHz 12 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 6 MHz 12 MHz
X 1 1 1 0 0 0 0 0 0
X X 0 0 0 0 0 0 0 0
Semiconductor Group
6-33
On-Chip Peripheral Components C501
6.3.3.2
Using Timer 2 to Generate Baud Rates
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note then the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts timer 2 into its baud rate generator mode, as shown in figure 6-18.
Figure 6-18 Timer 2 in Baud Rate Generator Mode The baud rate generator mode is similar to the auto-reload mode, in that rollover in TH2 causes the timer 2 registers to be reloaded with the 16-bit value in registers RC2H and RC2L, which are preset by software. Now the baud rates in modes 1 and 3 are determined by timer 2's overflow rate as follows: Modes 1, 3 baud rate = timer 2 overflow rate/16
Semiconductor Group
6-34
On-Chip Peripheral Components C501
The timer can be configured for either "timer" or "counter" operation: In the most typical applications, it is configured for "timer" operation (C/T2 = 0). "Timer" operation is a little different for timer 2 when it's being used as a baud rate generator. Normally, as a timer it would increment every machine cycle (thus at fOSC/12). As a baud rate generator, however, it increments every state time (fOSC/2). In that case the baud rate is given by the formula Modes 1,3 baud rate = fOSC/32x[65536 - (RC2H, RC2L)] where (RC2H, RC2L) is the content of RC2H and RC2L taken as a 16-bit unsigned integer. Note that the rollover in TH2 does not set TF2, and will not generate an interrupt. Therefore, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX can be used as an extra external interrupt, if desired. It should be noted that when timer 2 is running (TR2 = 1) in "timer" function in the baud rate generator mode, one should not try to read or write TH2 or TL2. Under these conditions the timer is being incremented every state time, and the results of a read or write may not be accurate. The RC registers may be read, but shouldn't be written to, because a write might overlap a reload and cause write and/or reload errors. Turn the timer off (clear TR2) before accessing the timer 2 or RC registers, in this case.
Semiconductor Group
6-35
On-Chip Peripheral Components C501
6.3.4 Details about Mode 0 Serial data enters and exists through RxD. TxD outputs the shift clock. 8 data bits are transmitted/ received: (LSB first). The baud rate is fixed at fOSC/12. Figure 6-19 shows a simplyfied functional diagram of the serial port in mode 0. The associated timing is illustrated in figure 6-20. Transmission is initiated by any instruction that uses SBUF as a destination register. The "Write to SBUF" signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "Write to SBUF", and activation of SEND. SEND enables the output of the shift register to the alternate output function line of P3.0, and also enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1 and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register are shifted to the right one position. As data bits shift out to the right, zeroes come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initialy loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeroes. This condition flags the TX control block to do one last shift and then deactivate SEND and set TI. Both of these actions occur at S1P1 of the 10th machine cycle after "Write to SBUF". Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX control unit writes the bits 1111 1110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bit comes in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set.
Semiconductor Group
6-36
On-Chip Peripheral Components C501
Internal Bus 1
Write to SBUF S D CLK Zero Detector
Shift
Q SBUF
&
RXD P3.0 Alt. Output Function
Start Baud Rate S6 Clock TX Control TX Clock TI
Shift Send
_ <1
&
Serial Port Interrupt REN RI & Start
_ <1
TXD P3.1 Alt. Output Function
Shift Clock RI RX Control
Receive
RX Clock
1 1 1 1 1 1 1 0 Shift RXD P3.0 Alt. Input Function
Input Shift Register Load SBUF Shift
SBUF Read SBUF Internal Bus
MCS02101
Figure 6-19 Serial Interface, Mode 0, Functional Diagram Semiconductor Group 6-37
SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456
Semiconductor Group
Transmit
D1 D4 D2 D3 D7 D5 D6
ALE
Write to SBUF
Send
S6P2
Shift
RXD (Data Out)
D0
Figure 6-20 Serial Interface, Mode 0, Timing Diagram
TXD (Shift Clock)
6-38
D0 D1 D2 D3 D4 D5 S5P
TI
S3P1 S6P1
Write to SCON (Clear RI)
RI
Receive
Receive
Shift D6 D7
RXD (Data In)
TXD (Shift Clock)
MCT02102
On-Chip Peripheral Components C501
On-Chip Peripheral Components C501
6.3.5 Details about Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. The baud rate is determined either by the timer 1 overflow rate, or the timer 2 overflow rate, or both (one for transmit and the other for receive). Figure 6-21 shows a simplified functional diagram of the serial port in mode 1. The assiociated timings for transmit receive are illustrated in figure 6-22. Transmission is initiated by an instruction that uses SBUF as a destination register. The "Write to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission starts at the next rollover in the divideby-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "Write to SBUF" signal). The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeroes are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeroes. This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "Write to SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divideby-16 counter is immediately reset, and 1FFH is written into the input shift register, and reception of the rest of the frame will proceed. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at latest 2 of the 3 samples. This is done for the noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection or false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which in mode 1 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1) RI = 0, and 2) Either SM2 = 0, or the received stop bit = 1 If either of these two condtions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bit goes into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD.
Semiconductor Group
6-39
On-Chip Peripheral Components C501
Internal Bus 1
Write to SBUF S D CLK Zero Detector Q SBUF &
_ <1
TXD
Start / 16 Baud Rate Clock / 16 Sample 1-to-0 Transition Detector RX Start TX Clock Serial Port Interrupt
Shift TX Control TI
_ <1
Data Send
RI RX Control
Load SBUF
1FFH Shift Bit Detector RXD Load SBUF
Input Shift Register (9Bits) Shift
SBUF Read SBUF Internal Bus
MCS02103
Figure 6-21 Serial Interface, Mode 1, Functional Diagram Semiconductor Group 6-40
TX Clock
Semiconductor Group
Transmit D1 D2 D3 D4 D6 D7 D5 Stop Bit Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
MCT02104
Write to SBUF
Send
Data
S1P1
Shift
Figure 6-22 Serial Interface, Mode 1, Timing Diagram
TXD
Start Bit
D0
6-41
TI
/ 16 Reset
RX Clock
RXD
Bit Detector Sample Times
On-Chip Peripheral Components C501
Receive
Shift
RI
On-Chip Peripheral Components C501
6.3.6 Details about Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in mode 2 (When bit SMOD in SFR PCON (87H) is set, the baud rate is fOSC/32). Mode 3 may have a variable baud rate generated from either timer 1 or 2 depending on the state of TCLK and RCLK (SFR T2CON). Figure 6-23 shows a functional diagram of the serial port in modes 2 and 3. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. The associated timings for transmit/receive are illustrated in figure 6-24. Transmission is initiated by any instruction that uses SBUF as a destination register. The "Write to SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission starts at the next rollover in the divideby-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "Write to SBUF" signal.) The transmision begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeroes are clocked in. Thus, as data bits shift out to the right, zeroes are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeroes. This conditon flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "Write to SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divideby-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bit come from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and to set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) RI = 0, and 2) Either SM2 = 0 or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bit goes into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxDTxD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8 or RI.
Semiconductor Group
6-42
On-Chip Peripheral Components C501
Internal Bus TB8
Write to SBUF S D CLK Zero Detector Q SBUF &
_ <1
TXD
Start / 16 Baud Rate Clock / 16 Sample 1-to-0 Transition Detector
Stop Bit Shift Generation TX Control TI
_ <1
Data Send
TX Clock Serial Port Interrupt
RX Clock Start RX Control
RI
Load SBUF Shift
1FF
Bit Detector RXD Load SBUF
Input Shift Register (9Bits) Shift
SBUF Read SBUF Internal Bus
MCS02105
Figure 6-23 Serial Interface, Mode 2 and 3, Functional Diagram Semiconductor Group 6-43
TX Clock
Write to SBUF
Semiconductor Group
Transmit
D1 D2 D3 D4 D7 D5 D6 TB8 Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit
MCT02587
Send
Mode 2 : S6P1 Mode 3 : S1P1
Data
Shift
TXD
Start Bit
D0
Figure 6-24 Serial Interface, Mode 2 and 3, Timing Diagram
TI
6-44
Stop Bit Gen.
/ 16 Reset
RX Clock
RX
Start Bit
On-Chip Peripheral Components C501
Receive
Bit Detector
Sample Times
Shift
RI
Interrupt System C501
7
Interrupt System
The C501 provides 6 interrupt sources with two priority levels. Four interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2 and serial interface), and two interrupts may be triggered externally (P3.2/INT0 and P3.3/INT1). This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers. Figure 7-25 gives a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections.
High Priority Timer 0 Overflow TF0 TCON.5 ET0 IE.1 Timer 1 Overflow TCON.0 TF1 TCON.7 ET1 IE.3 Timer 2 Overflow P1.1/ T2EX EXEN2 T2CON.3 USART TF2 T2CON.7 EXF2 T2CON.6 RI SCON.0 TI SCON.1 P3.2/ INT0 IT0 TCON.0 P3.3/ INT1 IT1 TCON.2
_ <1 _ <1
Low Priority PT0 IP.1
PT1 IP.3
ET2 IE.5
PT2 IP.5
ES IE.4 IE0 TCON.1 EX0 IE.0 IE1 TCON.3 EX1 IE.2 EA IE.7
PS IP.4
PX0 IP.0
PX1 IP.2
MCS01783
Figure 7-25 Interrupt Structure
Semiconductor Group
7-1
Interrupt System C501
7.1
Interrupt Registers
7.1.1 Interrupt Enable Register Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable register IE (interrupt enable) or T2CON. This register also contains the global disable bit (EA), which can be cleared to disable all interrupts at once. Generally, after reset all interrupt enable bits are set to 0. That means that the corresponding interrupts are disabled. Special Function Register IE (Address A8H) MSB AFH EA Reset Value : 0X000000B LSB A8H EX0 IE
Bit No. A8H
AEH -
ADH ET2
ACH ES
ABH ET1
AAH EX1
A9H ET0
The shaded bit is not used for interrupt control.
Bit EA
Function Enable/disable all interrupts. If EAL=0, no interrupt will be acknowledged. If EAL=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Not implemented. Reserved for future use. Timer 2 overflow / external reload interrupt enable. If ET2 = 0, the timer 2 interrupt is disabled. If ET2 = 1, the timer 2 interrupt is enabled. Serial channel (USART) interrupt enable If ES = 0, the serial channel interrupt 0 is disabled. If ES = 1, the serial channel interrupt 0 is enabled. Timer 1 overflow interrupt enable. If ET1 = 0, the timer 1 interrupt is disabled. If ET1 = 1, the timer 1 interrupt is enabled. External interrupt 1 enable. If EX1 = 0, the external interrupt 1 is disabled. If EX1 = 1, the external interrupt 1 is enabled. Timer 0 overflow interrupt enable. If ET0 = 0, the timer 0 interrupt is disabled. If ET0 = 1, the timer 0 interrupt is enabled. External interrupt 0 enable. If EX0 = 0, the external interrupt 0 is disabled. If EX0 = 1, the external interrupt 0 is disabled.
- ET2
ES
ET1
EX1
ET0
EX0
Semiconductor Group
7-2
Interrupt System C501
Special Function Register T2CON (Address C8H) MSB CFH TF2
Reset Value : 00H LSB C8H
Bit No. C8H
CEH EXF2
CDH RCLK
CCH
CBH
CAH TR2
C9H
TCLK EXEN2
C/T2 CP/RL2 T2CON
The shaded bits are not used for interrupt enable control.
Bit EXEN2
Function Timer 2 External Enable. When set, allows a capture or reload to occur as a result of a negative transition on pin T2EX (P1.1) if timer 2 is not being used to clock the serial port. EXEN2 = 0 causes timer 2 to ignore events at T2EX.
Semiconductor Group
7-3
Interrupt System C501
7.1.2 Interrupt Request / Control Flags The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the flag that generated this interrupt is cleared by the hardware when the service routine is vectored too, but only if the interrupt was transition-activated. lf the interrupt was level-activated, then the requesting external source directly controls the request flag, rather than the on-chip hardware. The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set by a rollover in their respective timer/counter registers. When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored too. Special Function Register TCON (Address 88H) MSB 8FH TF1 Reset Value : 00H LSB 88H IT0 TCON
Bit No. 88H
8EH TR1
8DH TF0
8CH TR0
8BH IE1
8AH IT1
89H IE0
The shaded bits are not used for interrupt control.
Bit TF1
Function Timer 1 overflow flag Set by hardware on timer/counter 1 overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 overflow flag Set by hardware on timer/counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine. External interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when processor vectors to interrupt routine. External interrupt 1 level/edge trigger control flag If IT1 = 0, low level triggered external interrupt 1 is selected. If IT1 = 1, falling edge triggered external interrupt 1 is selected. External interrupt 0 request flag Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when processor vectors to interrupt routine. External interrupt 0 level/edge trigger control flag If IT0 = 0, low level triggered external interrupt 0 is selected. If IT0 = 1, falling edge triggered external interrupt 0 is selected.
TF0
IE1
IT1
IE0
IT0
Semiconductor Group
7-4
Interrupt System C501
The timer 2 interrupt is generated by the logical OR of bit TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software. The serial port interrupt is generated by a logical OR of flag RI and TI in SFR SCON. Neither of these flags is cleared by hardware when the service routine is vectored too. In fact, the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, and the bit will have to be cleared by software. Special Function Register T2CON (Address C8H) Special Function Register SCON (Address. 98H) MSB CFH TF2 9FH SM0 Reset Value : 00H Reset Value : 00H LSB C8H T2CON
Bit No. C8H Bit No. 98H
CEH EXF2 9EH SM1
CDH RCLK 9DH SM2
CCH
CBH
CAH TR2 9AH RB8
C9H
TCLK EXEN2 9CH REN 9BH TB8
C/T2 CP/RL2 99H TI 98H RI
SCON
The shaded bits are not used for interrupt request control.
Bit TF2
Function Timer 2 Overflow Flag. Set by a timer 2 overflow. Must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. Timer 2 External Flag. Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1, SFR T2MOD) Serial interface transmitter interrupt flag Set by hardware at the end of a serial data transmission. Must be cleared by software. Serial interface receiver interrupt flag Set by hardware if a serial data byte has been received. Must be cleared by software.
EXF2
TI
RI
Semiconductor Group
7-5
Interrupt System C501
7.1.3 Interrupt Priority Register Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFR IP (Interrupt Priority, 0: low priority, 1: high priority).
Special Function Register IP (Address B8H) MSB 7 -
Reset Value : XX000000B LSB 0 PX0 IP
Bit No. B8H
6 -
5 PT2
4 PS
3 PT1
2 PX1
1 PT0
The shaded bits are not used for interrupt control.
Bit - PT2 PS PT1 PX1 PT0 PX0
Function Not implemented. Reserved for future use. Timer 2 Interrupt Priority Level. If PT2 = 0, the Timer 2 interrupt has a low priority. Serial Channel Interrupt Priority Level. If PS = 0, the Serial Channel interrupt has a low priority. Timer 1 Overflow Interrupt Priority Level. If PT1 = 0, the Timer 1 interrupt has a low priority. External Interrupt 1 Priority Level. If PX1 = 0, the external interrupt 1 has a low priority. Timer 0 Overflow Interrupt Priority Level. If PT0 = 0, the Timer 0 interrupt has a low priority. External Interrupt 0 Priority Level. If PX0 = 0, the external interrupt 0 has a low priority.
Semiconductor Group
7-6
Interrupt System C501
7.2
Interrupt Priority Level Structure
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 7-8 below: Table 7-8 Priority-within-Level Structure Interrupt Source External Interrupt 0, Timer 0 Interrupt, External Interrupt 1, Timer 1 Interrupt, Serial Channel, Timer 2 Interrupt, IE0 TF0 IE1 TF1 RI or TI TF2 or EXF2 Priority High
Low
Semiconductor Group
7-7
Interrupt System C501
7.3
How Interrupts are Handled
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1. An interrupt of equal or higher priority is already in progress. 2. The current (polling) cycle is not in the final cycle of the instruction in progress. 3. The instruction in progress is RETI or any write access to registers IE or IP. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IE or IP, then at least one more instruction will be executed before any interrupt is vectored too; this delay guarantees that changes of the interrupt status can be observed by the CPU. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests. The polling cycle/LCALL sequence is illustrated in figure 7-26.
C1 S5P2
C2
C3
C4
C5
Interrupt is latched
Interrupts are polled
Long Call to Interrupt Vector Address
Interrupt Routine
MCT01859
Figure 7-26 Interrupt Response Timing Diagram
Semiconductor Group
7-8
Interrupt System C501
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7-26 then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed. Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, while in other cases it does not; then this has to be done by the user's software. The hardware clears the external interrupt flags IE0 and IE1 only if they were transition-activated. The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the program counter with an address that depends on the source of the interrupt being vectored too, as shown in the following table 7-9. Table 7-9 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH Interrupt Request Flags IE0 TF0 IE1 TF1 RI / TI TF2 / EXF2
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the two top bytes from the stack and reloads the program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level. A simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of the same or lower priority level would be acknowledged.
Semiconductor Group
7-9
Interrupt System C501
7.4
External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition activated by setting or clearing bit IT0, respectively in register TCON. If ITx = 0 (x = 0 or 1), external interrupt x is triggered by a detected low level at the INTx pin. If ITx = 1, external interrupt x is negative edge-triggered. In this mode, if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx=1 then requests the interrupt. If the external interrupt 0 or 1 is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1.1/T2EX but only if bit EXEN2 is set. Since the external interrupt pins are sampled once in each machine cycle, an input high or low should be held for at least 6 oscillator periods to ensure sampling. lf the external interrupt is transition-activated, the external source has to hold the request pin high for at least one cycle, and then hold it low for at least one cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set (see figure 7-27). The external interrupt request flags will automatically be cleared by the CPU when the service routine is called.
Figure 7-27 External Interrupt Detection
Semiconductor Group
7-10
Interrupt System C501
7.5
Interrupt Response Time
If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be next instruction to be executed. The call itself takes two cycles. Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request was blocked by one of the three previously listed conditions. If an interrupt of equal or higer priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles since the longest instructions (MUL and DIV) are only 4 cycles long; and, if the instruction in progress is RETI or a write access to registers IE or IP the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction, if the instruction is MUL or DIV). Thus a single interrupt system, the response time is always more than 3 cycles and less than 9 cycles.
Semiconductor Group
7-11
Power Saving Modes C501
8
Power Saving Modes
The C501 provides two basic power saving modes : - - 8.1 Idle mode Power down mode. Power Saving Mode Control Register
The two power saving modes are controlled by bits which are located in the special function registers PCON. The SFR PCON is located at SFR address 87H. The bits PDE and IDLE in SFR PCON select the power down mode or the idle mode, respectively. If the power down mode and the idle mode are set at the same time, power down takes precedence. Furthermore, register PCON contains two general purpose flags. For example, the flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle. Then an instruction that activates idle can also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. Special Function Register PCON (Address 87H) Bit No. MSB 7 87H SMOD Reset Value : 0XXX0000B LSB 0 IDLE PCON
6 -
5 -
4 -
3 GF1
2 GF0
1 PDE
The function of the shaded bit is not used for power saving mode control.
Symbol - GF1 GF0 PDE IDLE
Function Reserved for future use General purpose flag General purpose flag Power down enable bit When set, starting of the power down mode is enabled Idle mode enable bit When set, starting of the idle mode is enabled
Semiconductor Group
8-1
Power Saving Modes C501
8.2
Idle Mode
In the idle mode the oscillator of the C501 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, and all timers are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The reduction of power consumption, which can be achieved by this feature depends on the number of peripherals running. If all timers are stopped and the serial interfaces are not running, the maximum power reduction can be achieved. This state is also the test condition for the idle mode ICC. So, the user has to take care which peripheral should continue to run and which has to be stopped during idle mode. Also the state of all port pins - either the pins controlled by their latches or controlled by their secondary functions - depends on the status of the controller when entering idle mode. Normally, the port pins hold the logical state they had at the time when the idle mode was activated. If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on. This applies to the serial interface in case it cannot finish reception or transmission during normal operation. The control signals ALE and PSEN are hold at logic high levels. As in normal operation mode, the ports can be used as inputs during idle mode. Thus a capture or reload operation can be triggered, the timers can be used to count external events, and external interrupts will be detected. The idle mode is a useful feature which makes it possible to "freeze" the processor's status - either for a predefined time, or until an external event reverts the controller to normal operation, as discussed below. The watchdog timer is the only peripheral which is automatically stopped during idle mode. The idle mode is entered by setting the flag bit IDLE (PCON.0). Note: PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle mode is obtained by byte-handling instructions, as shown in the following example: ORL PCON,#00000001B ;Set bit IDLE
The instruction that sets bit IDLE is the last instruction executed before going into idle mode. There are two ways to terminate the idle mode: - The idle mode can be terminated by activating any enabled interrupt. This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLE. - The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still running, the hardware reset must be held active only for two machine cycles for a complete reset.
Semiconductor Group
8-2
Power Saving Modes C501
8.3
Power Down Mode
In the power down mode, the on-chip oscillator is stopped. Therefore all functions are stopped; only the contents of the on-chip RAM and the SFR's are maintained. The port pins controlled by their port latches output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power-down mode. ALE and PSEN hold at logic low level (see table 9-1). The power-down mode is entered by setting the flag bit PDE (PCON.1). Note: PCON is not a bit-addressable register, so the above mentioned sequence for entering the power down mode is obtained by a byte-handling instruction, as shown in the following example: ORL PCON,#00000010B ;Set bit PDE
The instruction that sets bit PDE is the last instruction executed before going into power down mode. The only exit from power down mode is a hardware reset. Reset will redefine all SFR's, but will not change the contents of the internal RAM. In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level, before the power down mode is terminated. The reset signal that terminates the power down mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset).
Semiconductor Group
8-3
Power Saving Modes C501
8.4
State of Pins in Software Initiated Power Saving Modes
In the idle mode and in the power down mode the port pins of the C501 have a well defined status which is listed in the following table 8-10. This state of some pins also depends on the location of the code memory (internal or external). Table 8-10 : Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Internal Code Memory Idle ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 High High Data Data Data Data/alternate outputs Power Down Low Low Data Data Data Data/last output Last Instruction Executed from External Code Memory Idle High High Data Data Address Data/alternate outputs Power Down Low Low Float Data Data Data/last output
Semiconductor Group
8-4
OTP Memory Operation C501
9
OTP Memory Operation of the C501-1E
The C501-1E is the OTP version of the C501-1R ROM version microcontroller. Its functionality is fully compatible with the C501-1R functionality. This chapter describes in detail the programming features of the C501-1E. 9.1 Programming Modes
The C501-1E is programmed by usng a modified Quick-Pulse Programming TM 1) algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The C501-1E contains two signature bytes that can be read and used by a programming system to identify the device. The signature bytes identify the manufacturer and the type of the device. Table 9-11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. Table 9-11 OTP Programming Modes Mode Read signature Program code data Verify code data Progam encryption table Program security bit 1 Program security bit 2 Notes :
1. 2. 3. 4. "0" = valid low for that pin, "1" = valid high for that pin. VPP = 12.75 V 0.25V VCC = 5 V 10% during programming and verification. ALE/PROG receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for 100 s ( 10 s) and high for a minimum of 10 s.
RESET 1 1 1 1 1 1
PSEN 0 0 0 0 0 0
ALE/ PROG 1 0 1 0 0 0
EA/VPP 1 VPP 1 VPP VPP VPP
P2.7 0 1 0 1 1 1
P2.6 0 0 0 0 1 1
P3.7 0 1 1 1 1 0
P3.6 0 1 1 0 1 0
1
Quick-Pulse ProgrammingTM is a trademark phrase of Intel Corporation
Semiconductor Group
9-1
OTP Memory Operation C501
9.2
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in figure 9-28. Note that the C501-1E is running with a 4 to 6 MHz oscillator The reason the oscillator needs to be running is that the device is executing internal address and program data transfers.
+5 V
A0 - A7 1 1 1
Port 1
C501-1E
RESET P3.6 P3.7 XTAL2 4 - 6 MHz XTAL1
VCC
Port 0 EA/VPP ALE/PROG PSEN P2.7 P2.6 Programming Data +12.75 V 25 x 100 s Low Pulses 0 1 0 A8 - A12
VSS
P2.0 - P2.4
MCS03232
Figure 9-28 C501-1E OTP Memory Programming Configuration The address of the OTP memory location to be programmed is applied to port 1 and 2. The code byte to be programmed into that location is applied to port 0. RESET, PSEN and pins of port 2 and 3 specified in table 9-11 are held at the "Program code data" levels. The ALE/PROG signal is pulsed low 25 times as shown in figure 9-29.
25 Pulses ALE/PROG
10 s min. ALE/PROG 1 0
MCT03234
Figure 9-29 C501-1E ALE/PROG Waveform
Semiconductor Group
9-2
OTP Memory Operation C501
Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoots. 9.3 Encryption Table
The encryption table feature of the C501-1E is a feature that protects the program code in the OTP memory from being easily read by anyone other than the programmer. The encryption table is 32 byte of code that is exclusive NORed with the OTP memory data as it is read out. The first byte is XNORed with the first location read, the second with the second read, etc. through the 32nd byte read. The 33rd read byte is XNORED with the first byte of the encryption table, the 34rd with the second, etc. and so on in 32-byte groups. After the encryption table has been programmed, the user has to know its contents in order to correctly decode the program code stored in the OTP memory. The encryption table itself cannot be read out. For programming of the encryption table, the 25 pulse programming sequence must be repeated for addresses 0 through 1FH, using the "Program encryption table" levels. After the encryption table is programmed, verification cycles will produce only encrypted data. 9.4 Security Bits
There are two security bits on the C501-1E that, when set, prevent the OTP program memory from being read out or programmed further. For programming of the security bits, the 25 pulse programming sequence must be repeated using the "Program security bit" levels as specified in table 9-11. After the first security bit is programmed, further programming of the OTP memory and the encryption table is disabled. However, the other security bit can still be programmed. With only security bit one programmed, the OTP memory can still be read out for program verification. After the second security bit is programmed, it is no longer possible to read out (verify) the OTP memory content.
Semiconductor Group
9-3
OTP Memory Operation C501
9.5
OTP Memory Verification
If security bit 2 has not been programmed, the on-chip OTP program memory can be read out for program verification. The address of the OTP program memory locations to be read is applied to ports 1 and 2 as shown in figure 9-30. The other pins are held at the "Verify code data" levels indicated in table 9-11. The contents of the address location will be emitted on port 0. External pullups are required on port 0 for this operation.
+5 V
A0 - A7 1 1 1
Port 1
VCC
C501-1E
RESET P3.6 P3.7 XTAL2 4 - 6 MHz XTAL1 Port 0 EA/VPP ALE/PROG PSEN P2.7 P2.6
10 k Programming Data 1 1 0 0 Enable 0 A8 - A12
VSS
P2.0 - P2.4
MCS03235
Figure 9-30 C501-1E OTP Memory Verification If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the SIgnature Bytes The signature bytes are read by the same procedure as a normal verification of locations 30H and 31H, except that P3.6 and P3.7 need to be pulled to a logic low level. The values of the signature bytes are : Address 30H : E0H indicates manufacturer Address 31H : 71H indicates C501-1E
Semiconductor Group
9-4
Device Specifications C501
10
Device Specifications
10.1 Absolute Maximum Ratings Ambient temperature under bias (TA) ......................................................... Storage temperature (Tstg) .......................................................................... Voltage on VCC pins with respect to ground (VSS) ....................................... Voltage on any pin with respect to ground (VSS) ......................................... Input current on any pin during overload condition..................................... Absolute sum of all input currents during overload condition ..................... Power dissipation........................................................................................ - 40 to 85 C - 65 C to 150 C - 0.5 V to 6.5 V - 0.5 V to VCC +0.5 V - 10 mA to 10 mA I 100 mA I TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Semiconductor Group
10-1
Device Specifications C501
10.2 DC Characteristics for C501-L / C501-1R
VCC = 5 V + 10 %, - 15 %; VSS = 0 V;
Parameter Symbol
TA = 0 C to 70 C for the SAB-C501 TA = - 40 C to 85 C for the SAF-C501
Limit Values min. max. 0.2 VCC - 0.1 V 0.2 VCC - 0.3 V 0.2 VCC + 0.1 V V V V V V V V - - - - - - 0.5 - 0.5 - 0.5 Unit Test Condition
Input low voltage (except EA, VIL RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12 MHz 7) Idle mode, 12 MHz 7) Active mode, 24 MHz 7) Idle mode, 24 MHz 7) Active mode, 40 MHz 7) Idle mode, 40 MHz 7) Power Down Mode Notes see page 10-4
VIL 1 VIL 2 VIH VIH 1 VIH 2 VOL VOL 1 VOH VOH 1
0.2 VCC + 0.9 VCC + 0.5 0.7 VCC 0.6 VCC - - 2.4 0.9 VCC 2.4 0.9 VCC - 10 - 65 - -
VCC + 0.5 VCC + 0.5
0.45 0.45 - - - - - 50 - 650 1 10
IOL = 1.6 mA 1) IOL = 3.2 mA 1) IOH = - 80 A, IOH = - 10 A IOH = - 800 A 2), IOH = - 80 A 2) VIN = 0.45 V VIN = 2 V
0.45 < VIN < VCC
IIL ITL ILI CIO
A A A pF
fC = 1 MHz, TA = 25 C VCC = 5 V, 4) VCC = 5 V, 5) VCC = 5 V, 4) VCC = 5 V, 5) VCC = 5 V, 4) VCC = 5 V, 5) VCC = 2 ... 5.5 V 3)
ICC ICC ICC ICC ICC ICC IPD
- - - - - - -
21 4.8 36.2 8.2 56.5 12.7 50
mA mA mA mA mA mA A
Semiconductor Group
10-2
Device Specifications C501
10.3 DC Characteristics for C501-1E
VCC = 5 V + 10 %, - 15 %; VSS = 0 V;
Parameter Input low voltage (except EA/VPP, RESET) Input low voltage (EA/VPP) Input low voltage (RESET) Input high voltage (except XTAL1, EA/VPP, RESET) Input high voltage to XTAL1 Symbol
TA = 0 C to 70 C for the SAB-C501 TA = - 40 C to 85 C for the SAF-C501
Limit Values min. max. 0.2 VCC - 0.1 V 0.1 VCC - 0.1 V 0.2 VCC + 0.1 V V V V V V V V - - - - - - 0.5 - 0.5 - 0.5 Unit Test Condition
VIL VIL 1 VIL 2 VIH VIH 1
0.2 VCC + 0.9 VCC + 0.5 0.7 VCC 0.6 VCC - - 2.4 0.9 VCC 2.4 0.9 VCC - 10 - 65 - -
VCC + 0.5 VCC + 0.5
0.45 0.45 - - - - - 50 - 650 1 10
Input high voltage to EA/VPP, VIH 2 RESET Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE/PROG, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE/PROG, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA/VPP) Pin capacitance Power supply current: Active mode, 12 MHz 7) Idle mode, 12 MHz 7) Active mode, 24 MHz 7) Idle mode, 24 MHz 7) Power Down Mode Notes see next page.
VOL VOL 1 VOH VOH 1
IOL = 1.6 mA 1) IOL = 3.2 mA 1) IOH = - 80 A, IOH = - 10 A IOH = - 800 A 2), IOH = - 80 A 2) VIN = 0.45 V VIN = 2 V
0.45 < VIN < VCC
IIL ITL ILI CIO
A A A pF
fC = 1 MHz, TA = 25 C VCC = 5 V, 4) VCC = 5 V, 5) VCC = 5 V, 4) VCC = 5 V, 5) VCC = 2 ... 5.5 V 3)
ICC ICC ICC ICC IPD
- - - - -
21 18 36.2 20 50
mA mA mA mA A
Semiconductor Group
10-3
Device Specifications C501
Notes:
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall bellow the 0.9 VCC specification when the address lines are stabilizing.
2)
3)
IPD (Power Down Mode) is measured under following conditions: EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected. ICC (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; EA = Port0 = RESET= VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1 mA). ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VCC; all other pins are disconnected; ICC max at other frequencies is given by: active mode: ICC = 1.27 x fOSC + 5.73 idle mode: ICC = 0.28 x fOSC + 1.45 (C501-L and C501-1R only) where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.
4)
5)
7)
Semiconductor Group
10-4
Device Specifications C501
10.4 AC Characteristics for C501-L / C501-1R / C501-1E
VCC = 5 V + 10 %, - 15 %; VSS = 0 V
TA = 0 C to 70 C for the SAB-C501 TA = - 40 C to 85 C for the SAF-C501
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 12 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN max. - - - 233 - - 150 - 63 - 302 - Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. 2tCLCL - 40 max. - - - 4tCLCL - 100 - - 3tCLCL - 100 - ns ns ns ns ns ns ns ns ns ns ns ns Unit
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL
127 43 30 - 58 215 - 0 - 75 - 0
tCLCL - 40 tCLCL - 53
-
tCLCL - 25
3tCLCL - 35 - 0 -
tCLCL - 20
- 5tCLCL - 115 -
tCLCL - 8
- 0
*) Interfacing the C501 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
Semiconductor Group
10-5
Device Specifications C501
AC Characteristics for C501-L / C501-1R / C501-1E (cont'd) External Data Memory Characteristics Parameter Symbol 12 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 252 - 97 517 585 300 - 123 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. 6tCLCL - 100 6tCLCL - 100 max. - - - 5tCLCL - 165 - 2tCLCL - 70 8tCLCL - 150 9tCLCL - 165 3tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
400 400 30 - 0 - - - 200 203 43 33 433 33 -
tCLCL - 53
- 0 - - - 3tCLCL - 50 4tCLCL - 130
tCLCL - 40 tCLCL - 50
7tCLCL - 150
tCLCL + 40
- - - 0
tCLCL - 50
-
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 12 MHz min. Oscillator period High time Low time Rise time Fall time max. 285.7 ns ns ns ns ns Unit
tCLCL tCHCX tCLCX tCLCH tCHCL
83.3 20 20 - -
tCLCL - tCLCX tCLCL - tCHCX
20 20
Semiconductor Group
10-6
Device Specifications C501
10.5 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24
VCC = 5 V + 10 %, - 15 %; VSS = 0 V
TA = 0 C to 70 C for the SAB-C501 TA = - 40 C to 85 C for the SAF-C501
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 24 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN max. - - - 80 - - 60 - 32 - 148 - Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 2tCLCL - 40 max. - - - 4tCLCL - 87 - - 3tCLCL - 65 - ns ns ns ns ns ns ns ns ns ns ns ns Unit
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL
43 17 17 - 22 95 - 0 - 37 - 0
tCLCL - 25 tCLCL - 25
-
tCLCL - 20
3tCLCL - 30 - 0 -
tCLCL - 10
- 5tCLCL - 60 -
tCLCL - 5
- 0
*) Interfacing the C501 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
Semiconductor Group
10-7
Device Specifications C501
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont'd) External Data Memory Characteristics Parameter Symbol 24 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 118 - 63 200 220 175 - 67 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 6tCLCL - 70 6tCLCL - 70 max. - - - 5tCLCL - 90 - 2tCLCL - 20 8tCLCL - 133 9tCLCL - 155 3tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
180 180 15 - 0 - - - 75 67 17 5 170 15 -
tCLCL - 27
- 0 - - - 3tCLCL - 50 4tCLCL - 97
tCLCL - 25 tCLCL - 37
7tCLCL - 122
tCLCL + 25
- - - 0
tCLCL - 27
-
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 24 MHz min. Oscillator period High time Low time Rise time Fall time max. 285.7 ns ns ns ns ns Unit
tCLCL tCHCX tCLCX tCLCH tCHCL
41.7 12 12 - -
tCLCL - tCLCX tCLCL - tCHCX
12 12
Semiconductor Group
10-8
Device Specifications C501
10.6 AC Characteristics for C501-L40 / C501-1R40
VCC = 5 V + 10 %, - 15 %; VSS = 0 V
TA = 0 C to 70 C for the SAB-C501 TA = - 40 C to 85 C for the SAF-C501
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 40 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN max. - - - 55 - - 25 - 20 - 65 - Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz min. max. - - - 4 tCLCL- 45 - - 3 tCLCL- 50 - ns ns ns ns ns ns ns ns ns ns ns ns Unit
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL
35 10 10 - 10 60 - 0 - 20 - -5
2 tCLCL- 15 tCLCL- 15 tCLCL- 15
-
tCLCL- 15
3 tCLCL- 15 - 0 -
tCLCL- 5
- 5 tCLCL- 60 -
tCLCL- 5
- -5
*) Interfacing the C501 to devices with float times up to 25ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
Semiconductor Group
10-9
Device Specifications C501
AC Characteristics for C501-L40 / C501-1R40 (cont'd) External Data Memory Characteristics Parameter Symbol 40 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 75 - 38 150 150 90 - 40 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz min. 6 tCLCL- 30 6 tCLCL- 30 max. - - - 5 tCLCL- 50 - 2 tCLCL- 12 8 tCLCL- 50 9 tCLCL- 75 3 tCLCL+ 15 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
120 120 10 - 0 - - - 60 70 10 5 125 5 -
tCLCL- 15
- 0 - - - 3 tCLCL- 15 4 tCLCL- 30
tCLCL- 15 tCLCL- 20
7 tCLCL- 50
tCLCL+ 15
- - - 0
tCLCL- 20
-
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 40 MHz min. Oscillator period High time Low time Rise time Fall time max. 285.7 ns ns ns ns ns Unit
tCLCL tCHCX tCLCX tCLCH tCHCL
25 10 10 - -
tCLCL - tCLCX tCLCL - tCHCX
10 10
Semiconductor Group
10-10
Device Specifications C501
t LHLL
ALE
t AVLL t
LLIV
t PLPH t LLPL t PLIV
PSEN
t AZPL t LLAX
t PXAV t PXIZ t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Program Memory Read Cycle
Semiconductor Group
10-11
Device Specifications C501
t WHLH
ALE
PSEN
t LLDV t LLWL
RD
t RLRH
t RLDV t AVLL t LLAX2 t RLAZ
Port 0 A0 - A7 from Ri or DPL Data IN
t RHDZ t RHDX
A0 - A7 from PCL Instr. IN
t AVWL t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Data Memory Read Cycle
Semiconductor Group
10-12
Device Specifications C501
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Data Memory Write Cycle
t CLCL VCC- 0.5V
0.7 VCC 0.2 VCC- 0.1
0.45V
t CHCL
t CLCX t CLCH
t CHCX
MCT00033
External Clock Drive at XTAL2
Semiconductor Group
10-13
Device Specifications C501
10.7 ROM Verification Characteristics for C501-1R ROM Verification Mode 1 Parameter Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency Symbol min. Limit Values max. 48tCLCL 48tCLCL 48tCLCL 6 ns ns ns MHz - - 0 4 Unit
tAVQV tELQV tEHQZ
1/tCLCL
P1.0 - P1.7 P2.0 - P2.4
Address
t AVQV
Port 0
Data OUT
t ELQV
t EHQZ
P2.7 ENABLE
MCT00049
Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.4 = A8 - A12 Data: P0.0 - P0.7 = D0 - D7
Inputs: P2.5 - P2.6, PSEN = VSS ALE, EA = V IH RESET = V SS
ROM Verification Mode 1
Semiconductor Group
10-14
Device Specifications C501
10.8 OTP Programming and Verification Characteristics for C501-1E
VCC = 5 V 10%, VSS = 0 V, TA = 21 C to + 27 C
Parameter Programming supply voltage Programming supply current Oscillator frequency Address setup to ALE/PROG low Address hold after ALE/PROG Data setup to ALE/PROG low Data hold after ALE/PROG P2.7 (ENABLE) high to VPP VPP setup to ALE/PROG low VPP hold after ALE/PROG low ALE/PROG width Address to data valid ENABLE low to data valid Data float after ENABLE ALE/PROG high to ALE/PROG low Symbol min. VPP I PP 1 / tCLCL 12.5 - 4 48 tCLCL 48 tCLCL 48 tCLCL 48 tCLCL 48 tCLCL 10 10 90 - - 0 10 Limit Values max. 13.0 50 6 - - - - - - - 110 48 tCLCL 48 tCLCL 48 tCLCL - V mA MHz ns ns ns ns ns s s s ns ns ns s Unit
tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQV tEHQZ tGHGL
Semiconductor Group
10-15
Device Specifications C501
Programming P1.0 - P1.7 P2.0 - P2.4 Address
Verification Address
t AVQV
Port 0 Data Data
t DVGL t AVGL
ALE/PROG
t GHDX t GHAX
t GLGH t SHGL
t GHGL t GHSL
Logic 1 Logic 0
EA/ V PP
t EHSH
P2.7 ENABLE
t ELQV
t EHQZ
MCT03237
C501-1E OTP Memory Program/Read Cycle
Semiconductor Group
10-16
Device Specifications C501
AC Inputs during testing are driven at VCC - 0.5 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIHmin for a logic `1' and VILmax for a logic `0'. AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH / VOL level occurs. IOL / IOH 20 mA. AC Testing: Float Waveforms
Semiconductor Group
10-17
Device Specifications C501
Crystal Oscillator Mode
Driving from External Source
C
XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14
N.C.
3.5 - 40 MHz
XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14
C
XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15
External Oscillator Signal
XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15
MCS02452
C = 20 pF 10 pF (incl. stray capacitance)
Note : During programming and verification of the C501-1E OTP memory a clock signal of 4-6 MHz must be applied to the device. Recommended Oscillator Circuits
Semiconductor Group
10-18
Device Specifications C501
10.9 Package Outlines Plastic Package, P-DIP-40 for C501G-L / C501G-1R (Plastic Dual in-Line Package)
P-DIP-40 Package Outlines
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 10-19
Dimensions in mm
GPD05883
Device Specifications C501
Plastic Package, P-LCC-44 - SMD for C501G-L / C501G-1R / C501G-1E (Plastic Leaded Chip-Carrier)
P-LCC-44 Package Outlines
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 10-20
Dimensions in mm
GPL05882
Device Specifications C501
Plastic Package, P-MQFP-44 - SMD for C501G-L / C501G-1R (Plastic Metric Quad Flat Package)
P-MQFP-44 Package Outlines
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 10-21
Dimensions in mm
GPM05957
Index C501
11
Index
Note : Bold page numbers refer to the main definition part of SFRs or SFR bits.
A
Absolute maximum ratings . . . . . . . . . . 10-1 AC . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-6 AC characteristics . . . . . . . . . 10-5 to 10-13 ACC . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 ALE signal . . . . . . . . . . . . . . . . . . . . . . . 4-4
External bus interface . . . . . . . . . . . . . . ALE signal . . . . . . . . . . . . . . . . . . . . . Overlapping of data/program memory Program memory access . . . . . . . . . . Program/data memory timing. . . . . . . PSEN signal . . . . . . . . . . . . . . . . . . . . Role of P0 and P2 . . . . . . . . . . . . . . .
4-1 4-4 4-4 4-3 4-2 4-4 4-1
F
F0. . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-6 F1. . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-6 Features. . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Functional units . . . . . . . . . . . . . . . . . . . 1-1 Fundamental structure. . . . . . . . . . . . . . 2-1
B
B . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 Basic CPU timing . . . . . . . . . . . . . . . . . . 2-4 Block diagram. . . . . . . . . . . . . . . . . . . . . 2-1
C
C/T . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-17 C/T2 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-24 CP/RL2. . . . . . . . . . . . . . . . . . . . . 3-5, 6-24 CPU Accumulator . . . . . . . . . . . . . . . . . . . . 2-2 B register . . . . . . . . . . . . . . . . . . . . . . 2-3 Basic timing . . . . . . . . . . . . . . . . . . . . 2-4 Fetch/execute diagram . . . . . . . . . . . . 2-5 Functionality . . . . . . . . . . . . . . . . . . . . 2-2 Program status word. . . . . . . . . . . . . . 2-2 Stack pointer. . . . . . . . . . . . . . . . . . . . 2-3 CPU timing . . . . . . . . . . . . . . . . . . . . . . . 2-5 CY . . . . . . . . . . . . . . . . . . . . . . 2-3, 2-3, 3-6
G
GATE . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-17 GF0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 8-1 GF1 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 8-1
H
Hardware reset . . . . . . . . . . . . . . . . . . . 5-1 Hardware reset timing . . . . . . . . . . . . . . 5-2
I
I/O ports . . . . . . . . . . . . . . . . . . . 6-1 to 6-12 IDLE. . . . . . . . . . . . . . . . . . . . . . . . 3-5, 8-1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . 8-2 IE . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 7-2 IE0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-4 IE1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-4 INT0 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-10 INT1 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-10 Interrupts . . . . . . . . . . . . . . . . . . 7-1 to 7-11 Block diagram . . . . . . . . . . . . . . . . . . 7-1 Enable registers . . . . . . . . . . . . . . . . . 7-2 External interrupts . . . . . . . . . . . . . . 7-10 Handling procedure . . . . . . . . . . . . . . 7-8 Priority register . . . . . . . . . . . . . . . . . . 7-6 Priority within level structure . . . . . . . 7-7 Registers . . . . . . . . . . . . . . . . . 7-2 to 7-6 Request flags . . . . . . . . . . . . . . . . . . . 7-4 Response time . . . . . . . . . . . . . . . . . 7-11 Sources and vector addresses. . . . . . 7-9 IP . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 7-6 IT0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-4 IT1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-4
D
DC characteristics . . . . . . . . . . 10-2 to 10-4 DCEN . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-25 Device characteristics . . . . . . 10-1 to 10-21 DPH . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5 DPL . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5
E
EA. . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-2 Emulation concept . . . . . . . . . . . . . . . . . 4-5 ES. . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-2 ET0. . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-2 ET1. . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-2 ET2. . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-2 EX0. . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-2 EX1. . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-2 Execution of instructions . . . . . . . . 2-4, 2-5 EXEN2 . . . . . . . . . . . . . . . . . . 3-5, 6-24, 7-3 EXF2 . . . . . . . . . . . . . . . . . . . 3-5, 6-24, 7-5
L
Logic symbol . . . . . . . . . . . . . . . . . . . . . 1-2
Semiconductor Group
11-1
Index C501
M
M0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-17 M1 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-17 Memory organization . . . . . . . . . . . . . . . 3-1 Data memory . . . . . . . . . . . . . . . . . . . 3-2 General purpose registers . . . . . . . . . 3-2 Memory map. . . . . . . . . . . . . . . . . . . . 3-1 Program memory . . . . . . . . . . . . . . . . 3-2
PSEN signal. . . . . . . . . . . . . . . . . . . . . . 4-4 PSW. . . . . . . . . . . . . . . . . . . . . 2-3, 3-4, 3-6 PT0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-6 PT1 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-6 PT2 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-6 PX0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-6 PX1 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-6
R
RB8 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31 RC2H . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-23 RC2L . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-23 RCLK . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-24 RD . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 4-1 REN . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 RI . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31, 7-5 RS0 . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-6 RS1 . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-6 RxD . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-29
O
OTP memory operation . . . . . . . . 9-1 to 9-4 Encryption table . . . . . . . . . . . . . . . . . 9-3 Programming configuration. . . . . . . . . 9-2 Programming modes . . . . . . . . . . . . . 9-1 Programming waveform . . . . . . . . . . . 9-2 Security bits . . . . . . . . . . . . . . . . . . . . 9-3 Verification and signature bytes . . . . . 9-4 OV . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-6
P
P . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-6 P0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5 P1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5 P2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5 P3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5 Parallel I/O . . . . . . . . . . . . . . . . . 6-1 to 6-12 PCON . . . . . . . . . . . . . . . 3-4, 3-5, 6-32, 8-1 PDE . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 8-1 Pin configurations. . . . . . . . . . . . . 1-3 to 1-5 P-DIP-40 package . . . . . . . . . . . . . . . 1-4 P-LCC-44 package . . . . . . . . . . . . . . . 1-3 P-MQFP-44 package . . . . . . . . . . . . . 1-5 Pin definitions and functions. . . . 1-6 to 1-10 Ports . . . . . . . . . . . . . . . . . . . . . . 6-1 to 6-12 Alternate functions . . . . . . . . . . 6-8 to 6-9 Port loading and interfacing . . . . . . . 6-11 Port timing. . . . . . . . . . . . . . . . . . . . . 6-10 Quasi-bidirectional port structure Output driver circuitry . . . . . . . . . . . 6-4 Port 0/2 as address/data bus . . . . . 6-7 Read-modify-write function . . . . . . . . 6-11 Power down mode . . . . . . . . . . . . . . . . . 8-3 Power saving modes . . . . . . . . . . 8-1 to 8-4 Control register . . . . . . . . . . . . . . . . . . 8-1 Idle mode . . . . . . . . . . . . . . . . . . . . . . 8-2 Power down mode . . . . . . . . . . . . . . . 8-3 State of pins . . . . . . . . . . . . . . . . . . . . 8-4 PS. . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 7-6
S
SBUF . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-31 SCON . . . . . . . . . . . . . . 3-4, 3-5, 6-31, 7-5 Serial interface (USART) . . . . . 6-29 to 6-44 Baudrate generation. . . . . . . . . . . . . 6-32 with timer 1 . . . . . . . . . . . . . . . . . . 6-33 with timer 2 . . . . . . . . . . . . . . . . . . 6-34 Multiprocessor communication. . . . . 6-30 Operating mode 0 . . . . . . . . 6-36 to 6-38 Operating mode 1 . . . . . . . . 6-39 to 6-41 Operating mode 2 and 3 . . . 6-42 to 6-44 Registers . . . . . . . . . . . . . . . 6-30 to 6-31 SM0 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31 SM1 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31 SM2 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31 SMOD . . . . . . . . . . . . . . . . . . . . . 3-5, 6-32 SP . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5 Special function registers. . . . . . . 3-3 to 3-6 Table - address ordered. . . . . . 3-5 to 3-6 Table - functional order . . . . . . . . . . . 3-4
T
T0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 T1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 T2CON. . . . . . . . . . . 3-4, 3-5, 6-24, 7-3, 7-5 T2MOD . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-25 TB8 . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31 TCLK . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-24
Semiconductor Group
11-2
Index C501
TCON . . . . . . . . . . . . . . . 3-4, 3-5, 6-16, 7-4 TF0 . . . . . . . . . . . . . . . . . . . . . 3-5, 6-16, 7-4 TF1 . . . . . . . . . . . . . . . . . . . . . 3-5, 6-16, 7-4 TF2 . . . . . . . . . . . . . . . . . . . . . 3-5, 6-24, 7-5 TH0. . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-15 TH1. . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-15 TH2. . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-23 TI . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31, 7-5 Timer/counter . . . . . . . . . . . . . . . . . . . . 6-13 Timer/counter 0 and 1. . . . . . 6-14 to 6-21 Mode 0, 13-bit timer/counter . . . . . 6-18 Mode 1, 16-bit timer/counter . . . . . 6-19 Mode 2, 8-bit rel. timer/counter . . . 6-20 Mode 3, two 8-bit timer/counter. . . 6-21 Registers . . . . . . . . . . . . . . 6-15 to 6-17 Timer/counter 2. . . . . . . . . . . 6-22 to 6-28 Auto-reload mode DCEN=0 . . . . . 6-26 Auto-reload mode DCEN=1 . . . . . 6-27 Capture mode . . . . . . . . . . . . . . . . 6-28 Operating modes. . . . . . . . . . . . . . 6-22 Registers . . . . . . . . . . . . . . 6-23 to 6-25 TL0 . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-15 TL1 . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-15 TL2 . . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-23 TMOD. . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-17 TR0. . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-16 TR1. . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-16 TR2. . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-24 TxD. . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-29
W
WR . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 4-1
Semiconductor Group
11-3

▲Up To Search▲

Price & Availability of C501G-1E

	To Download C501G-1E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .